Xilinx vs. Intel: FPGA Market Leaders Launch Server Accelerator Cards
The two FPGA market leaders, Intel and Xilinx, both announced new accelerator cards this week designed to handle specialized, compute-intensive workloads and unburden already overworked CPUs in data center servers.
Xilinx today announced the Alveo U50 accelerator card, which the company said delivers between 10 and 20x improvements in throughput, latency and power efficiency for “domain-specific acceleration” of compute, network and storage workloads.
The U50 utilizes Xilinx’s UltraScale+ architecture and is the first Alveo product offered in a half-height, half-length form factor and 75-watt power envelope, according to Xilinx. The card has 8GB of high-bandwidth memory (HBM2), more than 400 GBps data transfer speeds, 100 gigabit/second networking connectivity and support for the PCIe Gen 4 and CCIX interconnects.
“By fitting into standard PCIe server slots and using one-third the power, the Alveo U50 significantly expands the scope in which adaptable acceleration can be deployed…,” the company said. “The high-speed networking I/O also supports advanced applications like NVMe-oF solutions (NVM Express over Fabrics), disaggregated computational storage and specialized financial services applications,” such as electronic trading and financial risk modeling, along with machine learning inference.
Salil Raje, EVP/GM of Xilinx’s Data Center Group, said “growing demands on the data center are pushing existing infrastructure to its limit, driving the need for adaptable solutions that can optimize performance across a broad range of workloads and extend the lifecycle of existing infrastructure, ultimately reducing TCO.”
For deep learning speech translation inferencing, Xilinx said the Alveo U50 delivers up to 25x lower latency, 10x higher throughput and lower power usage per node compared to GPU-only performance. When running the TPC-H Query benchmark for database query, Xilinx said the U50 delivers 4x higher throughput per hour and reduced operational costs by 3x compared to in-memory CPU performance.
In computational storage, Xilinx said the product delivers 20x more compression/decompression throughput and more than 30 percent less cost per node compared to CPU-only nodes, and for network acceleration of electronic trading, the U50 delivers 20x lower latency and sub-500ns trading time compared to CPU-only latency of 10us. Running Monte Carlo financial modeling grid computing simulations, Alveo U50 delivers 7x greater power efficiency compared to GPU-only performance.
“With the smaller design and advanced features of the Alveo U50, Xilinx is well positioned to expand the markets for acceleration with configurable logic,” said Karl Freund, senior analyst, HPC and deep learning, Moor Insights & Strategy. “The new Alveo U50 should allow them to break through the market noise with demonstrated and dramatic performance advantages in high-growth use cases.”
Xilinx industry partners AMD, IBM and Western Digital announced support for the product. Xilinx said OEMs are sampling the U50, general availability is scheduled for this fall.
Meanwhile, Intel has added the FPGA PAC D5005, the second card in its Programmable Acceleration Card portfolio, and announced that HPE is the first OEM to pre-qualify the card for use with HPE’s ProLiant DL3809 Gen 10 server. The card is based on an Intel Stratix 10 SX FPGA and is designed to provide workload acceleration to servers based on Intel Xeon Scalable processors using the Intel Acceleration Stack, which includes acceleration libraries and development tools.
Intel said the FPGA PAC D5005, when compared with Intel Arria 10 GX FPGA, delivers three times the programmable logic, up to 32 GB of DDR4 memory (a 4x increase) and faster Ethernet ports (two 100GE ports versus one 40GE port). “With a smaller physical and power footprint, the Intel PAC with Intel Arria 10 GX FPGA fits a broader range of servers, while the Intel PAC D5005 is focused on providing a higher level of acceleration,” the company said.
To make that happen, Intel needed to beef up the FPGA PAC D5005’s power and form factor. Whereas the single-slot Arria 10 GX FPGA is full height/half-length with a peak power rating of 70W, the two-slot PAC D5005 is full height/three-quarter length with a power rating of 215W.
The FPGA PAC D5005 targets compute-intensive applications such as streaming analytics, artificial intelligence (including speech to text), and media transcoding. “Data center customers use hardware accelerators for specific workloads that can most benefit from FPGA-based hardware acceleration,” the company said. “Diverting such tasks to tailored hardware accelerators offloads suitable workloads and frees a server’s CPU cycles for higher-value workloads. Offloading appropriate workloads lowers the data center operator’s total cost of ownership.”
While it’s been estimated that Xilinx has a roughly 60-40 FPGA market share lead over Intel, the overall market as of last year was sized at $1.8 billion, according to industry watcher Market Research Future, and is expected to rise at a CAGR of nearly 11 percent through 2025.