News & Insights for the AI Journey|Thursday, March 21, 2019
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Arm Unveils Neoverse Platforms for Cloud-to-Edge Computing 

Source: Arm

Following on its Neoverse roadmap announcement last October, Arm today revealed its next-gen Neoverse microarchitecture with compute and throughput-optimized silicon designs catered to general-purpose cloud and edge computing.

The Arm Neoverse N1 platform, the first built on the 7nm “Ares” core, scales up to 128 cores and delivers a 2.5x performance improvement on key cloud workloads, according to Arm. The company’s Neoverse E1 platform, also announced, debuts as a high-efficiency throughput platform, promising a 2.7x improvement in throughput performance over previous generations.

The new N1 platform (previously known by the Ares codename) is the successor to Arm’s 16nm Cosmos platform, which includes the Cortex-A72, A75 and A53 CPU cores. AWS’ Graviton processor, announced in November at AWS’ re:Invent conference, is based on Cosmos.

Arm reports that chips based on the N1 platform will boost integer performance by 60 percent over the Cortex-A72 Cosmos processor (measured with the industry SPEC int 2017 benchmark), overdelivering on their promise to improve performance by 30 percent year-to-year. N1 also yields a 30 percent power efficiency improvement over Cortex-A72, according to Arm.

“Going beyond raw compute performance, the Neoverse N1 platform was built from the ground up with infrastructure-class features, including server-class virtualization, state-of-the-art RAS support, power and performance management, and system level profiling,” commented Drew Henry, head of Arm’s infrastructure business unit — its fastest-growing division — in a blog post. “The platform also includes a coherent mesh interconnect, industry-leading power efficiency, and a compact design approach for tighter integration, enabling scaling from 4- to 128-cores.” Partners have the flexibility to add accelerators or other features with their own on-chip custom silicon, he added.

As you’d expect, Arm’s Coherent Mesh Network (CMN) is key technological asset of the N1 platform. “We’ve been making coherent interconnects for quite some time in different markets and have evolved from cross bar to a ring and now a mesh given the core counts that we’re at,” Senior Director Brian Jeff told reporters last week. “Ares and the CMN were designed together to optimize the way the mesh interconnect works together with the CPU and communicates about how much data to prefetch into memory, how the cache can be used and allocated among the different cores and a lot of other features.”

Jeff also noted, in a blog post offering a closer look at the microarchitecture, that the N1 system could scale beyond 128-cores, though “real systems will architect around memory bandwidth and likely come in at 64 to 96 cores with 8ch DDR4 and 96 to 128 cores with DDR5.” An 8-core chip at the edge is expected to draw <20 watts while a 128-core chip for hyperscale applications is estimated at <200 watts.

In a briefing last week, Henry, SVP and GM of Arm’s infrastructure business, noted the company’s rising momentum underscored by Top500 recognition in November for the world’s first petascale Arm supercomputer. Arm is also the engine for the massive post-K supercomputer, being built in Japan this year with Fujitsu AFX64 Arm CPUs. AWS, Huawei and Ampere have all announced Arm CPUs in recent months.

Market watchers have been looking for Arm’s traction in the larger datacenter market. “Everyone has wanted to know, ‘where are you guys in hyperscale, where are you in servers?'” Henry told reporters last week. With the rollout of AWS Neoverse Graviton and the launch of Arm’s N1 platform, Henry wants the industry to know that the success Arm has had in other areas of infrastructure is now moving into the core datacenter.

“The N1 platform is really about the core compute – the core compute you need in the hyperscale datacenter and the core compute you might need in the 5G base station or at an internet gateway,” said Henry. The Neoverse E1 platform, also announced today, “was designed very specifically to put high throughput through the internet, also from the edge to the core datacenter.”

“Featuring an intelligent design for highly-efficient data throughput, the Neoverse E1 achieves 2.7x more throughput performance, 2.4x more throughput efficiency, and over 2x more compute performance compared to our previous generations,” said Henry. “It also delivers scalable throughput for edge to core data transport, supporting everything from a sub-35W base station all the way through to a multi-100GB router.”

Both the N1 and E1 designs have been available to partners for “a while,” Arm said. The company expects the first silicon to come to market by the end of this year, ramping up into the following year, pending customers’ schedules and timelines.

This article originally appeared in sister publication HPCwire.

About the author: Tiffany Trader

With over a decade’s experience covering the HPC space, Tiffany Trader is one of the preeminent voices reporting on advanced scale computing today.

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