DARPA Upgrades Battlefield Simulations
The demands of training soldiers and pilots, a domain that is gradually incorporating AI-enabled technologies, has heightened the U.S. military’s need for far greater computing power. Hence, the Pentagon’s top research office is turning to HPC technologies to power souped-up simulators that could provide a far more realistic view of an increasingly electronic battlefield.
The Defense Advanced Research Projects Agency (DARPA) held a “Proposers’ Day” this week to gather ideas for implementing the HPC simulator initiative dubbed Digital RF Battlespace Emulator. The program seeks to create a new high-end computing category it calls “Real Time HPC” that balances computational horsepower with extremely low latency. The idea is to provide trainees with “a high-fidelity emulation of RF environments”—in other words, an electronic battlefield bristling with radars, sensors, communications and jammers.
The effort also underscores how machine intelligence is steadily making its way onto the battlefield. Among the early applications is applying AI to heavy contested radio-frequency spectrum. In one scenario, machine learning algorithms could be used to help emerging multipurpose RF gear share scarce spectrum while denying an adversary access to those airwaves.
The electromagnetic spectrum that support RF equipment “will be highly congested and contested,” according to industry watcher IHS Markit. “This is driving majority of innovations in radars and military communications.”
Hence, the HPC initiative seeks to take training and simulation a step further by creating what DARPA calls the “world’s first large-scale virtual RF test range.” Paul Tilghman, program manager for DARPA’s Microsystems Technology Office, noted that “existing computing technologies are unable to accurately model the scale, waveform interactions or bandwidth demands required to replicate real-world RF environments.”
Real-time HPC could help create simulators to test and train RF technologies and their users by providing “high-fidelity models of complex sensors systems,” Tilghman added.
At the processor level, DARPA managers said the initiative will seek to forge a new HPC architecture and “domain-specific hardware accelerators” that combine the processing power of GPUs and the low- latency attributes of FPGAs.
An architecture that incorporates the best traits of those chips would be augmented with development of interfaces, tools and hardware specifications needed to support integration of the HPC simulation platform and creation of a virtual RF test range. Those tools would be used, for example, to design various test scenarios while connecting the real-time simulator with existing training systems.
Tilghman noted the real-time HPC has applications beyond the RF emulator and virtual environments, including real-time data analytics that could be used for scientific research.
The Digital RF Battlespace Emulator is part of DARPA’s $1.5 billion Electronics Resurgence Initiative designed to promote basic research that can move processor technology beyond Moore’s Law scaling. The second phase of the chip initiative is focusing on specific applications. In the case of the HPC simulator, DARPA said that includes “bringing the benefits of domain specific processing architectures to defense systems.”
George Leopold has written about science and technology for more than 30 years, focusing on electronics and aerospace technology. He previously served as executive editor of Electronic Engineering Times. Leopold is the author of "Calculated Risk: The Supersonic Life and Times of Gus Grissom" (Purdue University Press, 2016).