Advanced Computing in the Age of AI | Friday, August 12, 2022

Avery Design Announces CXL 3.0 VIP 

TEWKSBURY, Mass., Aug. 3, 2022 — Avery Design Systems, the leader in functional verification solutions, today announced availability of CXL 3.0 VIP.  Computer Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices.  CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency.

“We continue to evolve and enhance our solution as new versions of CXL emerge. By offering a VIP and supporting verification solution in support of CXL 3.0 for the first wave of CXL 3.0 designs we can enable leading developers of server processors, managed DRAM and storage class memory (SCM) buffers, switch/retimer, and IP companies to rapidly meet the growing needs for the CXL datacenter ecosystem in 2022 and beyond,” said Chris Browy, vice president sales/marketing of Avery.  “Our collaboration with key ecosystem companies allows us to deliver best-in-class, robust CXL 3.0 VIP solutions that streamline the design and verification process and foster the rapid adoption of the CXL standard by the industry.”

Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe 6.0 and CXL 3.0 for CXL host, Type 1-3 devices, switches, and retimers.

The CXL 3.0 VIP adds key CXL 3.0 features including

  • Double the bandwidth using PCIe 6.0 PHY for 64 GT/s
  • Fabric capabilities
    • Multi-headed and fabric attached devices
    • Enhance fabric management
    • Composable disaggregated infrastructure
  • Improved capability for better scalability and resource utilization
    • Enhanced memory pooling
    • Multi-level switching
    • Direct memory/ Peer-to-Peer accesses by devices
    • New symmetric memory capabilities

The CXL 3.0 VIP also includes key features including

  • Additional CXL switch agent with fabric manager support
  • Support for AMBA® CHI to CXL/PCIe via CXS
  • Dynamic configuration of VIP for legacy PCIe, CXL 3.0, 2.0 or CXL 1.1 including CXL device types 1-3
  • Realistic traffic arbitration among CXL.IO, CXL.Cache, CXL.Mem and CXL control packets.
  • Unified user application data class for both pure PCIe and CXL traffic
  • Extension of the QEMU-CXL virtual platform environment for CXL 3.0/2.0 systems

Availability & Additional Resources

CXL VIP for CXL 3.0/2.0/1.1 is available today.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.


Source: Avery Design Systems

About the author: Tiffany Trader

With over a decade’s experience covering the HPC space, Tiffany Trader is one of the preeminent voices reporting on advanced scale computing today.

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