Advanced Computing in the Age of AI | Wednesday, May 18, 2022

Intel Extends IPU Roadmap Through 2026 

Intel is extending its roadmap for infrastructure processors through 2026, the company said at its Vision conference being held in Grapevine, Texas.

The company’s IPUs (infrastructure processing units) are megachips that are designed to improve datacenter efficiency by offloading functions such as networking control, storage management and security that were traditionally run on a host CPU. Intel is developing IPUs in close collaboration with infrastructure providers that include Google and Microsoft.

The IPUs will complement Xeon server chips but will also work with chips and accelerators based on other architectures such as Arm, said Sandra Rivera, executive vice president and general manager of the datacenter and AI group at the company, in an appearance during CEO Pat Gelsinger’s opening keynote on Tuesday.

Intel’s first IPU, called Mount Evans, was developed with Google, and will this year ship to Google and other service providers. Based on Arm Neoverse N1 cores, the 200Gbps ASIC platform has network and storage virtualization offloading features, and supports the NVM interface to emulate NVMe devices.

Also shipping this year is the second-generation FPGA-based 200 Gbps IPU called Oak Springs Canyon, which is built on the Xeon D server chip and the Agilex FPGA. The software-defined platform can be customized for networking and storage functions. It also has two 100 Gigabit Ethernet network interfaces and a crypto block. It will start shipping this year to select service providers, with wider deployments next year.

Next-generation 400Gbps parts follow. The ASIC IPU codenamed Mount Morgan is expected to ship in 2023 or 2024, and an FPGA-based IPU codenamed Hot Springs Canyon will ship in 2023, with broader deployments in 2024.

An 800GB version of an IPU is expected to ship in the 2025-2026 timeframe.

Source: Intel Corp.

Most of the major server chipmakers are developing a new class of SmartNIC-type chips to handle diverse datacenter functions. Nvidia has its BlueField data processing unit, or DPU, with Arm-based CPU chips and Mellanox networking components. AMD has hinted it will develop chips with its CPUs and technology from recently acquired Xilinx, and Pensando, which the company is in the process of acquiring.

Trends such as machine learning and the metaverse are driving the development of IPUs, said Rakesh Cheerla, director of software product management at Intel, during a break-out session at Vision.

The applications are distributed across thousands of nodes, and are broken up into microservices. The hardware enables raw processing capability, but software allows scale, which is important in adoption of the IPUs.

IPUs are custom built, which makes them more efficient for software pipelines and infrastructure workloads. They can be optimized for different use cases such as latency and throughput, and provide a secure and isolated environment for applications.

The software could be scaled for networking, storage, containers or other functional parts in an IPU, much of which depends on the requirements of customers.

“All of this requires us to build the next generation of digital infrastructure,” Cheerla said. “As we talk to customers, we realized that customers were looking more for the ability to run their own customized workflows,” he added.

Cheerla talked about an open-source development toolkit for IPUs called IPDK (Infrastructure Programmer Development Kit), which can be used to write applications for both x86 chips and Arm chips such as Marvell’s Octeon. The toolkit includes functional blocks to customize and define the workloads that could include offloading packet processing.

Source: Intel Corp.

The customer-specific IPUs are a part of Intel’s larger goal to develop custom chips for infrastructure providers and hyperscalers. Intel estimates about 85 percent of the datacenter infrastructure is based on Xeon CPUs. The company has also opened its doors for non-Intel intellectual property on chip platforms with the goal to get more chips made in its factories.

“I feel like I have more routes to market than I ever did while providing what they want, which is a compute platform that is ubiquitous. That gives them the durable capability to continue to provide scalable applications for their customers,” Rivera said during a press briefing.

About the author: Tiffany Trader

With over a decade’s experience covering the HPC space, Tiffany Trader is one of the preeminent voices reporting on advanced scale computing today.

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