Grovf Inc. Releases Low Latency RDMA RoCE V2 FPGA IP Core for Smart NICs
BERKELEY, Calif., Nov. 23, 2021 — Grovf Inc. has announced RDMA RoCE v2 IP core, a new product to democratize the RNIC market. RDMA RoCE v2 IP core is an FPGA IP and enables FPGA-based smart NIC producers and system integrators to develop and deploy RNIC use-cases.
“We’ve been working on this IP for more than a year and a half now to bring the RNIC enablement to FPGA-based NICs,” says Artavazd Khachatryan, CTO at Grovf. “Though the IP is built on FPGA, we have not compromised the latency and throughput compared to industry-leading ASIC based RNIC producers. ”Coupled with in-line offload and acceleration capability of FPGA, Grovf RDMA RoCE v2 IP will trigger applications such as storage clustering and disaggregation offload, HPC application offload, algorithmic trading, database memory pooling, and more.”
Features and benefits of the solution include
- 100Gbps line rate
- Under 2 usec latency
- Standard Verbs API support
- Compatibility to Channel Adapter and RoCE v2 requirements of Infiniband specification.
- Fully compatible with known RNIC products and soft RoCE implementations.
The RoCE v2 FPGA IP will be available for partners and interested customers starting from December 1, 2021.
GGrovf Inc. is an application acceleration and network offload company using FPGAs. Some of the company’s IP, such as Regexp, Probabilistic matching, Deep Packet Inspection (DPI), Network anomaly detection IP cores are among the fastest in the market. Currently, the company is focused on memory and storage disaggregation solutions over cache-coherent buses and data center networking technologies.
Source: Grovf Inc.