Advanced Computing in the Age of AI | Wednesday, August 17, 2022

AMD Unveils Speedier Chiplet Design With High-Bandwidth Interconnects 

Advanced Micro Devices is accelerating the GPU chiplet race with the release of a U.S. patent application for a device that incorporates high-bandwidth interconnects between processing elements.

AMD and Intel Corp. have each signaled their intent to pursue the chiplet approach, likely hastening the transition from mega-GPUs such as Nvidia’s Ampere graphics processor, industry observers note.

In a patent notification released on Dec. 31, 2020, AMD disclosed a GPU chiplet array that links processing elements via a high-speed interposer, or electrical interface, called a crosslink. According to the patent, the AMD design connects two GPU chiplets to a CPU using a traditional communications bus while a passive crosslink provides a bridge to a second GPU chiplet.

The link is described as a passive interposer die dedicated for “inter-chiplet communications,” according to the patent. It also partitions larger SoC functions into smaller processing tasks.

Chip analysts note the design also employs a “passive crosslink PHY,” or physical layer. “As the networks get more complex the links will have to be active,” said graphics industry analyst Jon Peddie. “I would imagine AMD and Intel have already built such [communications] systems.”

Source: AMD

Chiplet designs also are increasingly seen as a means of addressing the parallel nature of graphics processing. That and the fact that monolithic die designs are becoming ever more complex and expensive to fabricate. Breaking up processing components therefore requires robust component interconnects.

The company’s (NASDAQ: AMD) chiplet design employs crosslinks across memory, allowing faster access to cache levels. “This low-latency, inter-chiplet cache coherency in turn enables the chiplet-based system to operate as a monolithic GPU from the software developer's perspective,” AMD noted.

Chiplet-based designs, so called because they combine multiple components into a single package, are increasingly seen as addressing the inability of general-purpose CPUs to handle skyrocketing performance requirements. Lower-cost chiplets also address the need for workload-specific accelerators, proponents note.

Accelerated development by AMD, Intel, Nvidia and other chip makers also reflects efforts by groups such as the Open Compute Project to establish open interfaces and architectures that would permit mixing and matching chiplets from different vendors on individual SoC accelerators.

As development of chiplet GPUs advances, IC vendors have noted the difficulty of using current design tools for integrating individual components on a single chip package with high-bandwidth connections. “We need to make [chiplet] technology easier to use, and there is work we can do on the design methodology front to help with that,” Simon Segars, Arm’s chief executive, noted during a technology summit last year.

AMD noted in its patent disclosure that its passive die interposer deploys monolithic GPU functionality “in a manner that makes the chiplet implementation appear as a traditional monolithic GPU from a programmer model/developer perspective.”

“It makes total sense,” added Peddie, who considers Nvidia’s Ampere the likely end of the line for monster GPUs. “AMD and Intel have declared and shown they will follow the chiplet approach for their CPUs and GPUs.”

AMD's chiplet interconnect technology could find its way into HPE Cray supercomputers coming online next year at the Energy Department, noted Karl Freund of Moor Insights & Strategy.

--Editor's note: The story has been updated. 

About the author: George Leopold

George Leopold has written about science and technology for more than 30 years, focusing on electronics and aerospace technology. He previously served as executive editor of Electronic Engineering Times. Leopold is the author of "Calculated Risk: The Supersonic Life and Times of Gus Grissom" (Purdue University Press, 2016).

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