Intel Advances in DoD’s Chip Packaging Push
Developing new capabilities for integrating complex semiconductor devices such as chiplets into a single package is seen as one way of reviving the U.S. chip manufacturing. Recent funding proposals emphasize reshoring IC test, assembly and advanced packaging capabilities as a way of moving up the manufacturing learning curve after decades or outsourcing to Asian fabs.
That funding, much of it coming from Defense Department industrial base programs, is starting to flow.
Intel Corp. said this week it has been awarded a Pentagon contract for the second phase of an advanced packaging initiative called, SHIP, for State-of-the-art Heterogeneous Integrated Packaging. Intel was among a half-dozen contractors during a prototyping phase overseen by the Naval Surface Warfare Center, Crane Division.
The contract amount was not disclosed.
Intel said Friday (Oct. 2) the contract provides government access to its advanced chip packaging facilities in Arizona and Oregon. The SHIP program’s second phase will develop prototype multichip packages while advancing interface standards, protocols and security for advanced substrates linking heterogeneous silicon.
The resulting prototypes will integrate custom chips used in weapons systems with Intel’s ASICs, CPUs and FPGAs
“Heterogeneous assembly technology is a critical investment for both the DoD and our nation,” said Nicole Petta, principal director of DoD’s microelectronics office.
“The U.S. microelectronics industry is at an inflection point,” Ellen Lord, undersecretary of defense for acquisition and sustainment, told a DARPA chip summit in August. DoD is expanding its technology base efforts by implementing what Lord called a “step-by-step process for reconstituting the microelectronics supply chain,” focusing on advanced packaging and other manufacturing capabilities.
Along with Pentagon chip initiatives, a pending appropriations bill includes $5 billion to launch a manufacturing institute within the Commerce Department focused on chip packaging technology. Semiconductor test, assembly and packaging capabilities have steadily shifted to Asia, and IC packaging innovation is seen as one way to help secure chip supply chains—a priority for the U.S. military.
That proposed legislation also includes a $500 million investment fund to support a “domestic advanced microelectronics packaging ecosystem.”
The prototype phase of the SHIP program focused on reducing physical size, improving performance and chip reliability along with reducing power consumption and latency. The earlier phase also emphasized secure design tools required to integrate multiple heterogeneous devices in a single package, program officials said.
The second phase enables “diversifying [DoD’s] supply chain and protecting their intellectual property while also supporting ongoing semiconductor R&D in the U.S. and preserving critical capabilities onshore,” said Jim Brinker, president and general manager of Intel Federal.