Advanced Computing in the Age of AI | Thursday, June 30, 2022

Arm’s Segars Unwraps ‘5th Gen’ Computing Vision 

The simultaneous maturation of three technologies—AI, the Internet of Things and 5G wireless—are ushering in a data-driven 5th wave of computing underpinned by current cloud infrastructure, according to the chief executive of chip intellectual property vendor Arm.

Speaking at an annual Defense Department microelectronics summit, Simon Segars said new chip architectures are being designed around IoT sensors networks that will generate huge data volumes collected and transported by emerging 5G networks. Those massive data sets can then be used to train machine learning models to extract useful information via new AI algorithms.

As DoD seeks to revive U.S. chip manufacturing, drive semiconductor innovation and secure its microelectronics supply chain, “You have to think about the underlying technologies, the science that drives the next evolution of all of these technologies,” Segars told this week’s Electronics Resurgence Initiative (ERI) summit sponsored by the Defense Advanced Research Projects Agency (DARPA).

“And that’s an area where I think governments can play a big role in helping stimulate research—because this stuff is really hard.”

Simon Segars

Segars echoed growing bipartisan calls for rebooting western chip manufacturing after decades of offshoring. The pandemic has further exposed technology supply chain vulnerabilities, fueling concerns among military planners that DoD will lose access to leading edge IC manufacturing capabilities.

Another key issue at the annual DARPA conference is forging a post-Moore’s Law technology strategy. Among ERI’s goals is figuring out the semiconductor industry’s next move with the “run out of Moore’s Law,” said Stephen Welby, former assistant secretary of defense for research and engineering.

Hence, Arm and other chip designers are looking to new architectures to squeeze what is left from Moore’s Law and Dennard scaling.

“Physics gets in the way [and] you just can’t keep scaling transistors anymore,” Segars said. “So, you have to get really creative when it comes to architecture.” Adding another dimension via 3D integration and clever die packaging represent a possible path forward.

That approach has been used to develop chiplets in which individual dice are integrated into a single package with connections between them. Still, design challenges remain. “We need to make [chiplet] technology easier to use, and there is work we can do on the design methodology front to help with that,” Segars said.

Stacking memory, logic and analog components also would allow designers to pack more transistors into the same space, delivering greater performance and improved manufacturing yields. “This ability to go vertical, if we can simplify that, then I think that is going to unlock another dimension of performance,” the Arm CEO said.

The rise of IoT is also raising new concerns about chip security in billions of connected devices. A key requirement for securing IoT networks will be developing standards for hardening devices and growing the microelectronics ecosystem.

Arm previously devoted major resources to IoT security frameworks, including a "secure core" approach to bulletproofing the IoT that addressed network security at the microcontroller level.

“Security is probably the least well-defined aspect of technology,” Segar said. “It’s a changing landscape.” With the potential for deploying billions of potentially vulnerable IoT devices, “We need standards [for] how security is expressed,” he said. “You need to define what you are secured against.”

An IoT security framework driven by industry and government stakeholders would also help streamline product development so that industrial and sensor networks aren’t a hodge-podge of random devices with varying levels of security.

“We’re really trying to turn this into an industry thing,” said Segars.

About the author: George Leopold

George Leopold has written about science and technology for more than 30 years, focusing on electronics and aerospace technology. He previously served as executive editor of Electronic Engineering Times. Leopold is the author of "Calculated Risk: The Supersonic Life and Times of Gus Grissom" (Purdue University Press, 2016).

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