News & Insights for the AI Journey|Sunday, December 15, 2019
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Chiplet Effort Advances for Workload Acceleration 

Chiplet-based designs, so called because they combine multiple components into a single package, are increasingly seen as addressing the inability of general-purpose CPUs to handle skyrocketing performance requirements. Lower-cost chiplets have helped address the need for workload-specific accelerators, proponents note.

Those workload requirements prompted the Open Compute Project (OCP) to launch a chiplet design project in March 2019 aimed at an “open domain-specific architecture.” Among the goals is leveraging faster development and manufacturing attributes associate with chiplet accelerators.

The project reported progress this week, including steps toward define an open interface and architecture that permits the “mixing and matching” of chiplets from different vendors onto a single SoC accelerator.

Several interface specifications are being fleshed out to develop open paths between different chiplets, OCP reported on Thursday (Sept. 26). Among the candidates are physical layer, or PHY, -based technologies and a new interface approach descriptively dubbed “Bunch of Wires.”

The latter approach aims to “combine ease of design with process portability and suitability for use in low-cost packaging technologies,” OCP said. The group released an early specification this week during OCP summit. Group members include Aquantia, Avera Semi, Netronome and zGlue.

“We are observing new architectures emerging that solve for rapidly changing workloads currently not well-fit for a traditional large-scale integration approach to design,” said Aaron Sullivan, director of hardware engineering at Facebook (NASDAQ: FB).

“These new architectures provide improved approaches to rapidly and cost-effectively develop workload-specific products,” Sullivan added. “We believe an open chiplet-based architecture being developed within the [Open Domain-Specific Architecture] community provides a pathway towards achieving these goals, while enabling continued performance gains.”

The group is also working on link layers used to connect data and networks, a chiplet marketplace as well as prototype framework.

“Creating new open standards for chiplet-based architecture and interoperability is an important step forward to enabling emerging applications like machine learning that require compute resources at unprecedented scale,” added Kushagra Vaid, an engineer in Microsoft’s (NASDAQ: MSFT) Azure Hardware Infrastructure unit.

Market estimates for chiplet technology reflect growing demand for workload-specific accelerators. According to market watcher IHS/Informa, the aggregate market for chiplets is projected to be almost $3 billion by 2024, expanding to $10 billion by 2030.

About the author: George Leopold

George Leopold has written about science and technology for more than 30 years, focusing on electronics and aerospace technology. He previously served as executive editor of Electronic Engineering Times. Leopold is the author of "Calculated Risk: The Supersonic Life and Times of Gus Grissom" (Purdue University Press, 2016).

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