Advanced Computing in the Age of AI | Sunday, October 2, 2022

AI Supercomputer-on-a-Wafer Debuted by Cerebras 

Could wafer-scale silicon from Cerebras Systems be the first “supercomputer on a chip” worthy of the designation? Last week at Hot Chips at Stanford University, the Silicon Valley startup debuted the largest chip ever built, a 46,225 square millimeter wafer packing 1.2 trillion transistors. Cerebras says the chip’s 400,000 AI-optimized cores can train models 100-1,000 times faster than the current leading AI chip, Nvidia’s V100 GPU.

The Wafer Scale Engine is primarily an AI training machine aimed to harvest sparsity, so it’s not a supercomputing machine per se, but like other accelerators, it can work in tandem with and accelerate traditional modeling and simulation workloads. All three of the United States’ planned exascale-class supercomputers will support AI and data analytics capabilities.

To manufacture its Wafer Scale Engine, which is 57x larger than the current biggest chip (Nvidia’s GV100 GPU), Cerebras, working with TSMC’s 16-nm node, starts with a 300 mm wafer and removes the largest possible square, creating a single silicon chip with 400,000 sparse linear algebra cores, i.e., SLA cores, designed for sparse workloads like deep learning. The integration of these cores into a unified array on a single piece of silicon enables models to be trained in minutes, says Cerebras.

“We can map the entire neural network onto our compute array, we don’t put one layer, save it, another layer, save it. That allows us to achieve model parallel performance and scale linearly,” said Cerebras Founder and CEO Andrew Feldman in an interview with HPCwire. Feldman was the key figure behind Seamicro, which created the Atom-based microserver over a decade ago.

Cerebras’ wafer-scale engine has total of 18 gigabytes of on chip SRAM accessible within a single clock cycle, providing an aggregate 9 petabytes per second of memory bandwidth. An on-chip, all-hardware mesh-connected communication network delivers an aggregate bandwidth of 100 petabits per second.

Yield was one of the biggest challenges that Cerebras’ engineers, working closely with TSMC, had to overcome. Feldman counts it as one of the five major hurdles, along with cross-die connectivity, thermal expansion, packaging and cooling.

“Those were historically the five reasons why in the past 60 years, nobody could make one of these,” he said. “Cross-die connectivity and yield were the hardest. Once you’ve you succeeded, in that, you had to grapple with thermal expansion, packaging and cooling.”

Cerebras’ Wafer Scale Engine has 84 processing tiles acting as one device

Cerebras invented a technique as part of the lithographic process to lay thousands of communications links across every scribe line. The result, said Feldman, is that rather than behaving like one-hundred chips [84 specifically], the wafer-scale engine behaves like 400,000 cores. “The software has no knowledge of whether it’s on one chip or another chip; it just sees this array,” the CEO said. Cerebras collaborated with TSMC for more than two years to develop the necessary lithographic techniques.

Cerebras can reportedly yield every wafer that TSMC delivers; 100 percent yield. An array of repeated identical tiles is built into the wafer, resulting in 400,000 very small cores, enabling redundancy.

“When it comes to yield, redundancy is your friend,” said Sean Li, chief architect and co-founder, in his Hot Chips talk.

Only 1.5 percent of the overall die is dedicated to spare cores and links, and flaws can be circumvented using these spares.

The next challenge was getting this wafer-size chip onto a motherboard, and dealing with the coefficient of thermal expansion; in other words how do you prevent a silicon chip this size from cracking as the fiberglass printed circuit board expands? Cerebras says it invented a material and a new type of connector to absorb some of that difference even when the two elements were no longer plumb.

Cerebras Wafer Scale Engine (WSE) manufacturing process

Nearly every step of the manufacturing process had to be rethought and customized. “Now that we had the silicon connector, and a printed circuit board, we had another problem nobody else had ever encountered, which is nobody’s been able to package this,” said Feldman. “Nobody had a cold plate for it. Nobody knew how to design a PCB that was appropriate for it. And there were no tools in the manufacturing supply chain that allowed us to achieve the alignment we needed, that had the handling…. We had to invent tools that carried a wafer, we had to invent equipment to qualify and test whole wafers. We had to invent the software that did alignment, all of this so that we could yield a wafer. The final problem was how do you power and how do you cool it?”

The chip is too large for power or cooling to be sent across horizontally, so a third dimension, what Cerebras calls the Z dimension, was used in both cases. With this technique, power isn’t delivered across the PCB, it’s delivered through it. The PCBs have thousands of little holes, through-silicon-vias, and power is delivered through the via so the distance is not very far.

For cooling, rather than running cool water or air across it, cool water is punched down using a copper cold plate with a grid of tiny fins. Each die reticle cooling area contains about 100 fins, so that’s roughly 840 fins ferrying away the heat. The liquid drops down into a heat exchanger that uses air to cool the water. First-gen cold plate technology is not for the faint of heart, but Cerebras reports they’ve had it working “for years” now.

Cerebras has a full system under development and says it has been running customer workloads for months; its first customer shipment is scheduled for early September. Cerebras expects to reveal details of its system at Supercomputing in November with customers in the HPC/supercomputing space. The company reports it is currently clustering its wafer-scale chip nodes, using 100 Gigabit Ethernet.

Hopefully we’ll learn the clock speed of the chip as well as the power consumption for the complete system when it is announced. It’s been estimated that the chip will use 14-15 kilowatts of power, which isn’t unreasonable if it can really do the AI training work of 100-1,000 GPUs. As a point of comparison, the DGX-2 has a max power draw of 10 kilowatts — necessary to drive the 16 V100s, a couple Platinum Xeons, the NVSwitch, eight InfiniBand ports, plus NVMe storage.

Cerebras has been quietly developing its technology since 2015; it has secured $112 million in venture funding and has a staff of nearly 200. CEO Feldman, Chief Architect Sean Li, CTO Gary Lauterback and others in the core leadership team all hail from Seamicro, which was acquired by AMD in 2012 for $355 million.

“We got a little bit lucky in 2007, when Gary and I started Seamicro, but hardware was at a nadir in the valley. Every venture capitalist had their new guy from VMware, who just thought the answer was another virtual machine, and didn’t understand hardware at all. By 2016, we were back on the rise. And people understood that if you want to go fast, you need [better] hardware,” said Feldman.

“And so there was a willingness to engage in new architectures and willingness to engage in new system design, and that’s really important. I don’t think you can achieve the type of performance that we aspire to if you just build a chip; you’re going to put it in somebody else’s server, and you’re going to put your Ferrari in a Volkswagen chassis. And you’re going to get Volkswagen performance. If you want to build a Ferrari, you need to think about how to feed it. And its handling and its steering and every last aspect. And that’s why we’re system builders; that’s what we thought we needed to do to do this.”

About the author: Tiffany Trader

With over a decade’s experience covering the HPC space, Tiffany Trader is one of the preeminent voices reporting on advanced scale computing today.

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