AMD Launches Epyc Rome, First 7nm CPU
From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its 2nd generation Epyc Rome chips, based on its 7nm process technology. The new AMD Epyc 7002 series is a follow-on to the first-gen 14nm Epyc Naples CPUs, released in June 2017. The announcement marks a significant competitive step for AMD in its struggle to take market share from segment leader Intel. Intel meanwhile is preparing its 14nm Cooper Lake server chip line for launch in the first half of 2020 with 10nm Ice Lake to follow.
At the event held for press, analysts and partners, AMD emphasized its process leadership, a performance advantage over the Intel Cascade Lake line and put a sharp focus on security, which has been on a continuous news cycle since the Spectre/Meltdown vulnerabilities came to light over a year-and-a-half ago.
The 7002 processors feature up to 64 “Zen 2” cores per SOC, deliver up to 23 percent more instructions per clock (IPC) per core on server workloads and up to four times more L3 cache compared to the previous generation, said AMD. The company also reported that its 2nd gen server processors hold 80 world records, 15 of them in HPC, while delivering an estimated 25-50 percent lower TCO than competitive offerings.
“Adoption of our new leadership server processors is accelerating with multiple new enterprise, cloud and HPC customers choosing Epyc processors to meet their most demanding server computing needs,” said AMD CEO Lisa Su, noting that there are more than 60 Eypc-based platforms in the market today.
AMD says its next-generation AMD Infinity architecture gives customers access to the most I/O and memory bandwidth in its class, with 128 lanes of PCIe generation 4 (or more in custom builds). The upgraded Infinity fabric nearly doubles throughput, pushing 18GT/s socket-to-socket compared with 10.7 GT/s of throughput in the first generation chips.
In terms of security protection, the new chips are said to deliver “hardened at the core” features based on a silicon-embedded security subsystem and advanced features such as Secure Memory Encryption and Secure Encrypted Virtualization.
Market watcher Patrick Moorhead, Moor Insights & Strategy president and principal analyst, said the launch was a bigger leap forward than he had expected. “AMD improved most of its Gen 1 shortcomings like single-thread performance (+15 percent) and core scaling and added new RAS (uncorrectable DRAM error entry) and security (Secure Memory Encryption, Secure Encrypted Virtualization, 509 keys) capabilities, in addition to substantial, multi-core performance gains,” he shared.
Single-Sockets and Simplified SKU Stacks
In a pre-briefing held the evening before the launch, Scott Aylor, AMD’s Datacenter Solutions Group’s corporate VP/GM, underscored the momentum of the company’s single-socket strategy begun with the launch of first-gen Epyc two years ago. “With the current Epyc second generation technology, we will have the ability to address the entire two-socket market with our single-socket offering today for the first time ever,” said Aylor. “In our first generation, a fantastic start, we addressed about 50 percent of the addressable market with single-socket technology; now we’ve totally changed the trajectory of that with the second generation.”
Aylor also clarified that while there are dedicated dual- and single-socket SKUs, every Epyc first generation and second generation processor can be made single socket. “We choose to make some of those only single socket to drive our single socket agenda in the market,” he said.
AMD also emphasized the simplicity of its product stack. “We have a very simple, straightforward stack. Customers can choose the level of performance they want, the number of cores that they need for their application or workload, and procure that. No compromises. Because with the Epyc stack, all features are included in every Epyc processor. Every customer gets it all,” said AMD SVP Forrest Norrod during the launch.
Highlights of the nearly two-and-a-half hour event included HPE and Lenovo announcing the immediate availability of new platforms, with Lenovo being a major go-to-market partner to execute AMD’s single-socket strategy. Dell EMC, which launched single-socket first-gen Epyc-based PowerEdge servers last year, said it is planning to debut Rome platforms in the fall.
HPC partner Cray also showed up to support the launch. Cray CEO Pete Ungaro reviewed the company's big wins with AMD at Oak Ridge (Frontier) and at NERSC (Perlmutter) and announced that the U.S. Air Force Weather Agency will use a Cray Shasta system with 2nd gen Epycs to provide terrestrial and space weather information to the the Air Force and the U.S. Army.
AMD highlighted a number of HPC benchmarks in which it said its 64-core Epyc 7742 is outperforming Intel’s Xeon Platinum 28-core 8280 chip, noting up to 2x better performance in computational fluid dynamics and up to 72 percent higher performance for structural analysis (see slide above right, and endnotes for details). Further, in comparisons with Intel’s Xeon Platinum 8280L, AMD said Epyc 7742 achieved 97 percent higher performance in SpecRate 2017 (peak) integer workloads (source: link1, link2) and offered 88 percent faster SpecRate 2017 (peak) floating point performance (source: link1, link2).
Twitter Senior Director of Engineering Jen Frazer joined AMD’s Su on stage to report that the social media company is using the 2nd gen AMD Epyc to improve the TCO of its datacenters by 25 percent. Su’s admission that she is “a huge fan of Twitter” drew a collective chuckle from the audience, probably due to Su’s denial on Twitter the day before of rumors that she might join IBM as CEO.
Speaking of speculation, the buzz about Google potentially being a major launch partner panned out. Two hours into the proceedings, Su came back to the stage to welcome one final special guest. Bart Sano, Google’s vice president of platforms, revealed the web giant has deployed the 2nd gen AMD Epyc processors in its internal infrastructure production datacenter environment, marking the first Rome deployment of this kind. Sano also disclosed that by year end Google will support new general-purpose machines powered by the new chips on the Google Cloud Compute Engine.
The other big hyperscale partner at this launch was Microsoft Azure. Azure HBv2 instances, powered by Rome, are available today in preview and will support up to 36,000 cores for MPI workloads in a single virtual machine scale set, and up to 80,000 cores for larger customers, according to Evan Burness, principal program manager, Azure HPC.
Azure Corporate Vice President Girish Bablani reported that HBv2 VMs featuring 120 2nd Gen Epyc CPUs are demonstrating performance gains of over 100 percent on HPC workloads like fluid dynamics and automotive crash test analysis. HBv2 also marks the cloud’s first deployment of 200 Gigabit InfiniBand. Full availability for the upgraded instances is scheduled for Q4.
Benchmarking details for “Leadership Performance” slide
• Based on AMD internal testing of ESI VPS 2018.0, NEON4m benchmark, as of July 17, 2019 using a 2P EPYC 7742 powered reference server versus a 2P Xeon Platinum 8280 powered server. Results may vary.
• Based on AMD internal testing of Altair RADIOSS 2018, T10M benchmark, as of July 17, 2019 using a 2P EPYC 7742 powered reference server versus a 2P Xeon Platinum 8280 powered server. Results may vary.
• Based on AMD internal testing of LSTC LS-DYNA R9.3.0, neon benchmark, as of July 17, 2019 of a 2P EPYC 7742 powered reference server versus a 2P Xeon Platinum 8280 powered server. Results may vary.
• Based on AMD internal testing of Siemens PLM STAR-CCM+ 14.02.009, kcs_with_physics benchmark, as of July 17, 2019 using a 2P EPYC 7742 powered reference server versus a 2P Xeon Platinum 8280 powered server. Results may vary.
• Based on AMD internal testing of ANSYS FLUENT 19.1, lm6000_16m benchmark, as of July 17, 2019 of a 2P EPYC 7742 powered reference server versus a 2P Intel Xeon Platinum 8280 powered server. Results may vary.