AMD Verifies Its Largest 7nm Chip Design in Ten Hours
AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours.
The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. AMD scaled Calibre nmDRC on 4,140 cores across 69 HB virtual machines on an Azure cloud platform, powered by AMD’s own Epyc processors.
The ten-hour result represents a major reduction in total turnaround time for verification, even in the face of the Radeon Instinct Vega20’s complexity. AMD completed a second verification pass in approximately nine additional hours, for a total of two passes in 19 hours.
"AMD demands speed and quality of execution in our cutting-edge semiconductor design work, so achieving two verification passes in one day in the cloud is critical to getting future designs to market," said Daniel Bounds, senior director of AMD Datacenter Products. "AMD is pleased to see that Mentor's Calibre nmDRC scales on cloud-based AMD Epyc-powered servers not just in traditional use models, but also on the Azure public cloud."
AMD gives significant credit to Mentor for this accomplishment, citing improvements in scaling and memory consumption for Calibre that reduced memory requirements by up to 50 percent and enabled substantial cost savings in a key area. "Mentor continues to enhance our software solutions to help customers speed time-to-market, regardless of where they elect to run their physical verification," said Joe Sawicki, executive vice president of Mentor IC EDA.
Mentor, in turn, credited TSMC. Sawicki continued: "We are pleased to expand our collaboration with TSMC so our mutual customers running on third-party clouds can fully leverage both TSMC process technology and Mentor's software platforms, providing them with additional options to more quickly deliver ICs manufactured on TSMC's new processes."