DARPA, NSF Pursue Machine Learning Chip
A new U.S. research initiative seeks to develop a processor capable of real-time learning while operating with the “efficiency of the human brain.”
The National Science Foundation (NSF) and the Defense Advanced Research Projects Agency jointly announced a “Real Time Machine Learning” project on March 15 soliciting industry proposals for “foundational breakthroughs” in hardware required to “build systems that respond and adapt in real time.”
Andreas Olofsson of DARPA’s Microsystems Technology Office is overseeing the real-time ML initiative. Prior to joining DARPA, Olofsson headed Adepteva, where he oversaw development of the Epiphany-V, a 1,024-core, 64-bit RISC processor.
The 36-month machine learning project is the latest in a series of hardware-related efforts by DARPA focused on chip design and circuit design automation along with greater use of open-source components. Program officials said the ML program would “leverage these approaches to improve design efficiency and the ML innovation cycle by creating no-human-in-the-loop end to end hardware generators optimized for ML.”
The first of two research phases would focus on development of a machine learning hardware compiler that would be used to generate “state of the art” machine algorithms and networks based on existing ML programming frameworks (see chart).
A second 18-month development phase would extend early DARPA compiler work to parallel efforts at NSF while supporting “hardware optimization driven by system requirements,” according to the DARPA solicitation. “A fundamental component of the Phase 2 research will be to continue exploring the tradeoffs between system performance and efficiency for different machine learning architectures,” the agency said.
The two U.S. research agencies said their collaboration is designed to promote “cross-pollination” of real-time machine learning concepts being funded by both.
DARPA expects to release the first version of its real-time ML processor roughly halfway through the three-year effort, with chip tape-out beginning in Phase 2. The program would culminate in a version 2 release and a demonstration of working silicon, according to a program schedule.
DARPA said multiple research awards are planned, collectively expected to be worth about $10 million. Research proposals are due May 1, and the ML processor initiative is scheduled to launch with the new federal fiscal year on Oct. 1, 2019.
The NSF/DARPA solicitation is here.